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// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

module p5v_main_pwr
(
// ------------------------
// Clock and Reset signals
// ------------------------
	input       	iClk, //clock for sequential logic 
	input      		iRst_n, //reset signal from PLL Lock, resets state machine to initial state
// ----------------------------
// inputs and outputs
// ---------------------------- 
	input				iPWRGD_PS_PWROK_CPU_PLD_R,		//PS_PWROK from MB to indicate P12V_MAIN is ready
	input				iPWRGD_P5V_MAIN_SCM,			   //PWRGD from P5 MAIN VR
	
	output reg		oFM_P5V_MAIN_SCM_EN,				//To enable P5V MAIN VR
	output reg		oP5V_MAIN_PWR_FAULT			   //indicate SCM P5V MAIN VR fault, need to tunnel to CPU FPGA thru LVDS


);

//////////////////////////////////////////////////////////////////////////////////
// Parameters
//////////////////////////////////////////////////////////////////////////////////
   localparam  LOW =1'b0;
   localparam  HIGH=1'b1;
	
//////////////////////////////////////////////////////////////////////////////////
// Internal Signals
//////////////////////////////////////////////////////////////////////////////////
	reg         rPWRGD_P5V_MAIN_SCM_FF;
	
	reg         rP5V_MAIN_PWR_FAULT_FF;
	
//////////////////////////////////////////////////////////////////////////////////
// Secuencial Logic
//////////////////////////////////////////////////////////////////////////////////
   
   always @ ( posedge iClk or negedge iRst_n) begin
		if(!iRst_n) begin
			oFM_P5V_MAIN_SCM_EN				<= LOW;
			oP5V_MAIN_PWR_FAULT			   <= LOW;
			rP5V_MAIN_PWR_FAULT_FF        <= LOW;
			rPWRGD_P5V_MAIN_SCM_FF        <= LOW;

		end
			
		else begin
			rPWRGD_P5V_MAIN_SCM_FF		   <= iPWRGD_P5V_MAIN_SCM;
	
			rP5V_MAIN_PWR_FAULT_FF			<= ( oFM_P5V_MAIN_SCM_EN && rPWRGD_P5V_MAIN_SCM_FF	&&	!iPWRGD_P5V_MAIN_SCM)	? HIGH	: 	rP5V_MAIN_PWR_FAULT_FF;			
			oP5V_MAIN_PWR_FAULT				<=	rP5V_MAIN_PWR_FAULT_FF;
						
			oFM_P5V_MAIN_SCM_EN				<= iPWRGD_PS_PWROK_CPU_PLD_R;

			
		end
	end
	
endmodule
